Review of “Voltage-Clock Scaling for Low Energy Consumption in Real-time Embedded Systems” by

Yann-Hang Lee and C. M. Krishna.

Abstract

The CPU utilization is less in most of the modern day applications. To further improve the devices, power consumption is one the areas of research of a real time embedded system. When the processor runs on a low voltage the clock rate is slower and at higher voltages the clock rate is high. The energy consumption reduction is observed to be significantly high. Yann-Hang Lee and C. M. Krishna have reviewed various techniques and have proposed two algorithms to reduce the power consumption.

Motivation

Lot of real time embedded systems crave for low energy and power consumption. The potential applications like spacecrafts, satellites and battery operated devices would benefit a lot from a significant power reduction.

Observation

The main source of power consumption is due to the charging and discharging of parasitic capacitance. The power P is proportional to the frequency and square of supply voltage. The delay comes into the picture because the delay [1] increases when the supply voltage is reduced. The additional circuitry required to offset the noise increase also increases the delay.

Mr. Lee and Mr. Krishna have proposed two scheduling methods in the paper. They have assumed that real time embedded systems have scheduling on fixed priority. The processor can be run in high voltage fast clock (H mode) or low voltage slow clock (L mode) based on the tasks. This is done because the execution period will exceed deadline period if the processor is utilized in L mode only. From fig (1) we can see that when we run the processor in L mode only the execution time exceeds the deadline period. The time required to switch from L mode to H mode (Ts) is also considered.

The static approach assigns low power mode or high power mode based on calculation done before. Fig (1) shows that task t2 is run in H mode as it requires high processing time. Task t1 and t3 are run in L mode as they require lower processing period. Static method is easy to implement as the assignments of L mode and H mode is known before the execution of the process.

In dynamic approach the tasks are assigned L mode or H mode based on the workload. Fig (1) shows that the first three tasks are run in L mode and when the calculation is done based on past computational times the system assigns H mode to the last two tasks. Though static and dynamic approaches in the figure show that both of them consume same energy, it is different for most of the processes. The dynamic approach helps increase the power saving.

New Technique

Earlier techniques had proposed increasing the processor idle time by calculating the deadline time of a process. By completing tasks and switching activities within a deadline period the voltage could be reduced in the idle time [2]. For preemptive systems a technique was proposed that prioritizes tasks and executed tasks based on earliest deadline first [3]. For non preemptive systems a heuristic algorithm was proposed to minimize power by determining recourse allocation and task assignment [4]. But these techniques did not reduce power consumption significantly. The techniques introduced by Mr. Lee and Mr. Krishna estimates that the power consumption is reduced by 68% for an increase in processing time by 60%.

How the new technique is verified

Mr. Lee and Mr. Krishna have used ARM7D’s electrical characteristics to demonstrate the power consumption reduction. The processor is assumed to run 1.5 times faster in H mode than in L mode. The mean execution time is assumed to be 0.8 times the worst case execution time (WCET). The power consumption reduction is estimated to be around 65% based on certain factors.

References

[1] Yann-Hang Lee, C.M. Krishna. "Voltage-Clock Scaling for Low Energy Consumption in Real-Time Embedded Systems," rtcsa, p. 272, Sixth International Conference on Real-Time Computing Systems and Applications (RTCSA'99), 1999

[2] T. Ishihara and H. Yasuura, “Voltage scheduling problem for dynamically variable voltage processors,” International Symposium on Low Power Electronics and Design, Aug. 1998, pp. 197- 202.

[3] F. Yao, A. Demers, and A Shenker, “A scheduling model for reduced CPU energy,” IEEE Foundations of Computer Science, 1995, pp. 374-382.

[4] I. Hong, D. Kirovski, G. Qu, M. Potkonjak, and M. B. Srivastava, “Power optimization of variable voltage core-based systems,” Proceedings – Design Automation Conference, 1998, pp. 176- 181.