Review of The Simulation and Eva

Review of The Simulation and Evaluation of Dynamic Voltage Scaling Algorithms by Trevor Pering, Tom Burd, and Robert Brodersen

Abstract

The energy consumption reduction in microprocessors can be achieved by Dynamic Voltage Scaling (DVS). The algorithm is based on certain benchmarks. The DVS algorithm is implemented by a software control and the voltage is varied dynamically based on the performance requirements.

Motivation

The PDA class devices have functions like User Interface (UI), audio and mpeg playback. These devices use general processors and the processor has relatively high idle times. Trevor Pering, Tom Burd, and Robert Brodersen have simulated and evaluated DVS algorithm that reduces the energy consumption of these devices based on the benchmark.

Observation

By decreasing the supply voltage we can reduce the energy consumption, but the offset of this that we increase the delay. By DVS we give minimum clock frequency necessary without much latency. They have used 3 benchmarks to analyze the algorithms. User-Interface, Audio and MPEG are the benchmarks. Four algorithms are used to study these benchmarks - FLAT, COPT, PAST and AVG<weight>.

FLAT algorithm is without voltage scaling. The operating voltage is at a fixed level. This algorithm is used to calculate the power consumption with a fixed voltage.

Clipped Optimal (COPT) algorithm is a theoretical algorithm and is used to compare with realizable algorithms. The COPT algorithm calculates the minimum energy of a system for a given delay.

PAST algorithm is a realizable algorithm. The algorithm calculates the previous interval and dynamically changes the voltage and frequency. The limit of this algorithm is that it cannot be used on a system that is almost busy or idle for the present process to calculate delay for the next process.

AVG<weight> calculates the next average by taking into account the previous running average. The limit of this algorithm is that the results are dependent on the weight parameter.

The three benchmarks or events have different delay patterns. The UI event delays are dependent on the user and usually have short bursts of busy time. The audio events have even delays as the input data rate is constant and the processor job is to output data to external device. The MPEG decoding is done using inverse discrete cosine transform (IDCT). The processing time varies depending on the number of ICDTs. The frame period is fixed at 71ms.

New Technique

Trevor Pering, Tom Burd, and Robert Brodersen have analyzed four different algorithms to show the energy reduction using three events. The PAST and AVG<weight> algorithms are realizable algorithms. The FLAT algorithm is used to calculate energy consumption at different fixed voltage levels and COPT algorithm is used to calculate the minimum energy. By these we can compare the energy reduction on each benchmark. These algorithms can help decrease energy consumption in devices like PDA, storage audio players like ipod. And to add to this I would suggest adding a buffer before the processing. If the frame that is being processed is delayed beyond the deadline period the next frame could be stored in the buffer and the voltage-frequency can varied accordingly based on the buffer size being used.

How the new technique is verified

Trevor Pering, Tom Burd, and Robert Brodersen have verified the algorithms shown in figure 1 [1] using simulation based on ARM8 processor. The X axis is the Clipped delay ratio. The clipped delay ratio [1] is the delay of a task with a deadline α.

There is 20% reduction in energy consumption for an UI event with no increase in delay using COPT method and there was a 50% decrease in energy consumption for a delay factor of 1.2. Since audio has a steady data flow rate the energy consumption reduction was observed to be 84% using AVG algorithm. For a MPEG event the maximum energy reduction achievable was 24%.

We see from the results that we can further reduce the energy consumption by using buffers. This would need further research and a wider use of benchmarks as the devices like PDA, players and Hand held devices have added various other functions over years. But if we could find a solution, these devices would further improve their performance by increasing the duration of the activity without worrying about the battery going dead.

Voltage scaling was tested on UNIX workstations. The energy reduction could be calculated by analyzing the delay and voltage levels. Many DSP applications also use DVS algorithms as they have predictable workloads.

[1] Trevor Pering, Tom Burd, and Robert Brodersen, “The Simulation and Evaluation of Dynamic Voltage Scaling Algorithms”, In Proc. Int'l Symposium on Low Power Electronics and Design, pages pp. 76-81, Aug. 1998.