SimpleScalar Tool Set is an architecture simulator that reproduces the behavior of a computing device. It takes system inputs and produces system outputs and system metrics. Program codes written either in C or FORTRAN are compiled and executed by the simulator. The simulator tracks micro architecture state for each cycle and produces detailed history of all instructions executed.
Figure 1: Simplescalar Software Architecture - [1]
The advantages of the SimpleScalar tools are high flexibility, portability, extensibility and performance. Their flexibility is demonstrated by the inclusion of five processor simulators. These five are execution driven processor simulators for the SimpleScalar architecture, which range from an extremely fast functional simulator to a detailed out of order issue processor simulator that supports non blocking caches and speculative execution.
The SimpleScalar architecture is derived from the MIPS-IV ISA. The architecture is defined in ss.def, which contains a macro definition for each instruction in the instruction set. Each macro defines the opcode, name, flags, operand sources and destinations and actions to be taken for a particular instruction.
The instruction actions (which appear as macros) that are common to all simulators are defined in ss.h. Those actions that require different implementations in different simulators are defined in each simulator code file.
The processor simulators that accompany the tool set are
1. Functional Simulation: The fastest, least detailed simulator (sim-fast) resides in sim-fast.c. sim-fast does no time accounting: it executes each instruction serially, performing no instructions in parallel, sim-fast assumes no cache. A separate version of sim-fast, sim-safe, also performs functional simulation, but checks for correct alignment and access permissions for each memory reference. Both the versions are less than 300 lines of code making it very simple.
2. Cache Simulation: The SimpleScalar tool set comes with two cache simulators (sim-cache and sim-cheetah). These simulators are ideal for fast simulation of caches if effect of cache performance on execution time is not needed.
3. Profiling: The distribution comes with a functional simulator that produces voluminous and varied profile on instruction classes and addresses, text symbols, memory accesses, braches and data segment symbols.
4. Out- of-order processor timing simulation: The most complicated and detailed simulator (sim-outorder).The simulator supports out-of-order issue and execution, based on the Register Update Unit.
Apart from these, there are common files which are used by all simulators.
The utilities that accompany SimpleScalar are pipeline tracing and a source-level debugger.
[1] Todd Austin, Eric Larson, Dan Ernst, "SimpleScalar: An Infrastructure for Computer System Modeling", Computer, 2002 - ieeexplore.ieee.org